State of the art non-volatile memory devices are typically constructed by fabricating a field effect transistor in a silicon substrate. The field effect transistor is capable of storing electrical charge either in a separate gate electrode, known as a floating gate, or in a dielectric layer underlying a control gate electrode. Data is stored in a non-volatile memory device by changing the threshold voltage of the field effect transistor through the storage of electrical charge over the channel region of the substrate. For example, in an n-channel enhancement device, an accumulation of electrons in a floating gate electrode, or in a dielectric layer overlying the channel region, creates a high threshold voltage in the field effect transistor. When the control gate is grounded, current will not flow through the transistor, which is defined as a logic 0 state. Conversely, a reduction in the negative charge over the channel region creates a low threshold voltage, possibly negative. In this condition, with the control gate grounded, current will flow through the field effect transistor, which is defined as a logic 1 state.
One particular type of non-volatile memory device is the flash EEPROM (electrically-erasable-programmable-read-only-memory). Flash EEPROMs are a type of device which provide electrical erasing capability. The term "flash" refers to the ability to erase the memory cells simultaneously with electrical pulses. In an erased state, the threshold voltage of the field effect transistor is low and electrical current can flow through the transistor indicating a logic 1 state.
To program an EEPROM cell, typically, drain-side hot-electron injection is used to inject electrons onto either a floating gate electrode, or into trapping sites in a dielectric film overlying the channel region. The injection current can be enhanced by increasing either the channel electric field, or the electric field in the dielectric layer. To reduce the amount of time necessary to complete a programming operation, very high drain and gate voltages are used, such that the transistor is operating very close to breakdown during programming. However, the high voltages necessary for drain-side injection require that an additional power supply be provided to supply voltage levels in excess of the standard 5-volt operating voltage.
Breakdown conditions during programming can be avoided by injecting electrons from the source region, rather than the drain region. To program an EEPROM device using source-side injection, a select gate electrode is formed overlying a portion of the channel region adjacent to the source region. The select gate electrode is electrically isolated from the control gate electrode, which is formed adjacent to the drain region. During programming, an electric field gradient is established in the channel region such that electrons originating in the source region are accelerated across a potential drop, and are injected onto a floating gate electrode located below the control gate electrode. Programming with source side injection increases the longevity of an EEPROM device by reducing the stress on the dielectric layer as compared with the excessive electric fields used for drain-side injection. Additionally, it has been demonstrated that source-side injection can be many times more efficient than drain side injection. The higher efficiency reduces the amount of time necessary to perform a programming operation.
Although EEPROM devices using source-side injection offer enhanced programming ability and extended operating life, the construction of an EEPROM memory cell using source-side injection typically requires that three separate semiconductor layers be provided for the fabrication of a select gate, a control gate, and a floating gate. The necessity of providing three separate polysilicon layers for the fabrication of gate electrodes vastly increases the complexity of the fabrication process. Additionally, the necessity of placing three separate electrodes over the channel region increases the cell size of the EEPROM device. Accordingly, further advances in device design and fabrication are necessary to meet the demand for high-density EEPROM memory arrays.